1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of Related Art
FIGS. 8A and 8B show a sectional view and a plan view, respectively, of a semiconductor device of a related art. In a semiconductor device 100, a lower-layer interconnect 102 and an upper-layer interconnect 104 are connected by a via material or a via wire 106 (thereafter it is simply called a via). The via 106 is buried in a via hole. The via 106 is in contact with an end portion of the upper-layer interconnect 104. Incidentally, in FIGS. 8A and 8B, only the interconnects and the via hole are shown and insulating films on the periphery of the interconnects and the via are omitted.
The upper-layer interconnect 104 and the via 106 are formed by the dual damascene process. That is, after the formation of a trench for the upper-layer interconnect 104 and a hole for the via 106 by etching, the upper-layer interconnect 104 and the via 106 are formed by burying copper in the trench and the hole.
In FIG. 8B, the region where the via 106 is present is indicated by hatch lines. As is apparent from this figure, the via 106 has the shape of a square as plan viewed.
Incidentally, Patent Documents 1 and 2 can be mentioned as related arts.
[Patent Document 1] Japanese Patent Laid-Open No. 2005-327898
[Patent Document 2] Japanese Patent Laid-Open No. 2002-124575
In the dual damascene process, however, during etching there may sometimes occur a relative positional displacement between a trench for an interconnect and a hole for a via, reducing the area of a region where the two overlap. If the area of this region is too small, a burying imperfection occurs when the copper is buried in the above-described trench and hole.
FIG. 9A is an SEM photograph (a plan view) showing the appearance of upper-layer interconnects and via when there is scarcely any positional displacement. On the other hand, FIG. 9B is an SEM photograph showing the appearance of upper-layer interconnects and via when there is a positional displacement of approximately 20 nm. The interconnect width and interconnect intervals of the upper-layer interconnects are both approximately 90 nm. The length of the upper-layer interconnect is approximately 330 nm. The positional relationship between the upper-layer interconnects 112 and the via 114 in these photographs is schematically shown in FIG. 10.
If there is a positional displacement as shown in FIG. 9B, then a void 118 due to a burying imperfection of copper may sometimes occur as shown in FIG. 11. FIG. 11 is an SEM photograph (a sectional view) showing the appearance of the void 118 occurring within the via 114 in the vicinity of a lower-layer interconnect 116.